Modeling shared cache and bus in multi-cores for timing analysis
Proceedings of the 13th International Workshop on Software & Compilers for Embedded Systems
WCET analysis of instruction cache hierarchies
Journal of Systems Architecture: the EUROMICRO Journal
What to make of multicore processors for reliable real-time systems?
Ada-Europe'10 Proceedings of the 15th Ada-Europe international conference on Reliable Software Technologies
OPODIS'11 Proceedings of the 15th international conference on Principles of Distributed Systems
Memory-centric scheduling for multicore hard real-time systems
Real-Time Systems
PRETI: partitioned real-time shared cache for mixed-criticality real-time systems
Proceedings of the 20th International Conference on Real-Time and Network Systems
PDPA: period driven task and cache partitioning algorithm for multi-core systems
Proceedings of the 20th International Conference on Real-Time and Network Systems
Quality of service capabilities for hard real-time applications on multi-core processors
Proceedings of the 21st International conference on Real-Time Networks and Systems
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
A Unified WCET analysis framework for multicore platforms
ACM Transactions on Embedded Computing Systems (TECS)
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Memory accesses form an important source of timing unpredictability. Timing analysis of real-time embedded software thus requires bounding the time for memory accesses. Multiprocessing, a popular approach for performance enhancement, opens up the opportunity for concurrent execution. However due to contention for any shared memory by different processing cores, memory access behavior becomes more unpredictable, and hence harder to analyze. In this paper, we develop a timing analysis method for concurrent software running on multi-cores with a shared instruction cache. Communication across tasks is by message passing where the message mailboxes are accessed via interrupt service routines. We do not handle data cache, shared memory synchronization and code sharing across tasks. Our method progressively improves the lifetime estimates of tasks that execute concurrently on multiple cores, in order to estimate potential conflicts in the shared cache. Possible conflicts arising from overlapping task lifetimes are accounted for in the hit-miss classification of accesses to the shared cache, to provide safe execution time bounds. We show that our method produces lower worst-case response time (WCRT) estimates than existing shared-cache analysis on a real-world embedded application.