The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
An optimal memory allocation scheme for scratch-pad-based embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
The case for the reduced instruction set computer
ACM SIGARCH Computer Architecture News
Giotto: A Time-Triggered Language for Embedded Programming
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Computer Architecture: A Quantitative Approach
Computer Architecture: A Quantitative Approach
Schedulability Analysis of Periodic Fixed Priority Systems
IEEE Transactions on Computers
Design for Timing Predictability
Real-Time Systems
Supporting Demanding Hard-Real-Time Systems with STI
IEEE Transactions on Computers
An Esterel processor with full preemption support and its worst case reaction time analysis
Proceedings of the 2005 international conference on Compilers, architectures and synthesis for embedded systems
REMIC: design of a reactive embedded microprocessor core
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Software-based instruction caching for embedded processors
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
A Multithreaded Soft Processor for SoPC Area Reduction
FCCM '06 Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines
The case for the precision timed (PRET) machine
Proceedings of the 44th annual Design Automation Conference
A processor extension for cycle-accurate real-time software
EUC'06 Proceedings of the 2006 international conference on Embedded and Ubiquitous Computing
An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture
DS-RT '08 Proceedings of the 2008 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications
Time-predictable computer architecture
EURASIP Journal on Embedded Systems - FPGA supercomputing platforms, architectures, and techniques for accelerating computationally complex algorithms
Domain-Specific Language for HW/SW Co-design for FPGAs
DSL '09 Proceedings of the IFIP TC 2 Working Conference on Domain-Specific Languages
SyncCharts in C: a proposal for light-weight, deterministic concurrency
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Handling mixed-criticality in SoC-based real-time embedded systems
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Implementing time-predictable load and store operations
EMSOFT '09 Proceedings of the seventh ACM international conference on Embedded software
Tight WCRT analysis of synchronous C programs
CASES '09 Proceedings of the 2009 international conference on Compilers, architecture, and synthesis for embedded systems
A Single-Path Chip-Multiprocessor System
SEUS '09 Proceedings of the 7th IFIP WG 10.2 International Workshop on Software Technologies for Embedded and Ubiquitous Systems
Challenge benchmarks for verification of real-time programs
Proceedings of the 4th ACM SIGPLAN workshop on Programming languages meets program verification
Reactive parallel processing for synchronous dataflow
Proceedings of the 2010 ACM Symposium on Applied Computing
A disruptive computer design idea: architectures with repeatable timing
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Deterministic, predictable and light-weight multithreading using PRET-C
Proceedings of the Conference on Design, Automation and Test in Europe
Design choices for high-confidence distributed real-time software
ISoLA'10 Proceedings of the 4th international conference on Leveraging applications of formal methods, verification, and validation - Volume Part II
Temporal isolation on multiprocessing architectures
Proceedings of the 48th Design Automation Conference
Designing next-generation real-time streaming systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Handling timing constraints violations in soft real-time applications as exceptions
Journal of Systems and Software
How to enhance a superscalar processor to provide hard real-time capable in-order SMT
ARCS'10 Proceedings of the 23rd international conference on Architecture of Computing Systems
Worst-case execution time analysis-driven object cache design
Concurrency and Computation: Practice & Experience
Compiling for time predictability
SAFECOMP'12 Proceedings of the 2012 international conference on Computer Safety, Reliability, and Security
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
A hard real-time capable multi-core SMT processor
ACM Transactions on Embedded Computing Systems (TECS)
An instruction scratchpad memory allocation for the precision timed architecture
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Bounding WCET of applications using SDRAM with priority based budget scheduling in MPSoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Building timing predictable embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
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In a hard real-time embedded system, the time at which a result is computed is as important as the result itself. Modern processors go to extreme lengths to ensure their function is predictable, but have abandoned predictable timing in favor of average-case performance. Real-time operating systems provide timing-aware scheduling policies, but without precise worst-case execution time bounds they cannot provide guarantees. We describe an alternative in this paper: a SPARC-based processor with predictable timing and instruction-set extensions that provide precise timing control. Its pipeline executes multiple, independent hardware threads to avoid costly, unpredictable bypassing, and its exposed memory hierarchy provides predictable latency. We demonstrate the effectiveness of this precision-timed (PRET) architecture through example applications running in simulation.