LUSTRE: a declarative language for real-time programming
POPL '87 Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages
The ESTEREL synchronous programming language: design, semantics, implementation
Science of Computer Programming
The effectiveness of multiple hardware contexts
ASPLOS VI Proceedings of the sixth international conference on Architectural support for programming languages and operating systems
The embedded machine: predictable, portable real-time code
PLDI '02 Proceedings of the ACM SIGPLAN 2002 Conference on Programming language design and implementation
Microc/OS-II
Reliable and Precise WCET Determination for a Real-Life Processor
EMSOFT '01 Proceedings of the First International Workshop on Embedded Software
RTAS '99 Proceedings of the Fifth IEEE Real-Time Technology and Applications Symposium
Compiling for Fine-Grain Concurrency: Planning and Performing Software Thread Integration
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Virtual simple architecture (VISA): exceeding the complexity limit in safe real-time systems
Proceedings of the 30th annual international symposium on Computer architecture
Real-Time Objects on the Bare Metal: An Efficient Hardware Realization of the JavaTM Virtual Machine
ISORC '01 Proceedings of the Fourth International Symposium on Object-Oriented Real-Time Distributed Computing
Hardware support for real-time operating systems
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Towards direct execution of esterel programs on reactive processors
Proceedings of the 4th ACM international conference on Embedded software
RTSS '04 Proceedings of the 25th IEEE International Real-Time Systems Symposium
Supporting Demanding Hard-Real-Time Systems with STI
IEEE Transactions on Computers
The case for the precision timed (PRET) machine
Proceedings of the 44th annual Design Automation Conference
Predictable programming on a precision timed architecture
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A disruptive computer design idea: architectures with repeatable timing
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Temporal isolation on multiprocessing architectures
Proceedings of the 48th Design Automation Conference
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Certain hard real-time tasks demand precise timing of events, but the usual software solution of periodic interrupts driving a scheduler only provides precision in the millisecond range. NOP-insertion can provide higher precision, but is tedious to do manually, requires predictable instruction timing, and works best with simple algorithms To achieve high-precision timing in software, we propose instruction-level access to cycle-accurate timers. We add an instruction that waits for a timer to expire then reloads it synchronously. Among other things, this provides a way to exactly specify the period of a loop To validate our approach, we implemented a simple RISC processor with our extension on an FPGA and programmed it to behave like a video controller and an asynchronous serial receiver. Both applications were much easier to write and debug than their hardware counterparts, which took roughly four times as many lines in VHDL. Simple processors with our extension brings software-style development to a class of applications that were once only possible with hardware