A disruptive computer design idea: architectures with repeatable timing

Authors:
Stephen A. Edwards;Sungjun Kim;Edward A. Lee;Isaac Liu;Hiren D. Patel;Martin Schoeberl
Affiliations:
Columbia University;Columbia University;UC Berkeley;UC Berkeley;UC Berkeley;Vienna University of Technology
Venue:
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Year:
2009

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Abstract

This paper argues that repeatable timing is more important and more achievable than predictable timing. It describes microarchitecture approaches to pipelining and memory hierarchy that deliver repeatable timing and promise comparable or better performance compared to established techniques. Specifically, threads are interleaved in a pipeline to eliminate pipeline hazards, and a hierarchical memory architecture is outlined that hides memory latencies.