The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Latency-rate servers: a general model for analysis of traffic scheduling algorithms
IEEE/ACM Transactions on Networking (TON)
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
A Real-Time Streaming Memory Controller
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Time-predictable memory arbitration for a Java chip-multiprocessor
JTRES '08 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
A disruptive computer design idea: architectures with repeatable timing
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Improved Power Modeling of DDR SDRAMs
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
Memory Controllers for Real-Time Embedded Systems: Predictable and Composable Real-Time Systems
An Analyzable Memory Controller for Hard Real-Time CMPs
IEEE Embedded Systems Letters
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs
Proceedings of the Conference on Design, Automation and Test in Europe
Towards variation-aware system-level power estimation of DRAMs: an empirical approach
Proceedings of the 50th Annual Design Automation Conference
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Powering down SDRAMs at run-time reduces memory energy consumption significantly, but often at the cost of performance. If employed speculatively with real-time memory controllers, power-down mechanisms could impact both the guaranteed bandwidth and the memory latency bounds. This calls for power-down strategies that can hide or bound the performance loss, making run-time memory power-down feasible for real-time applications. In this paper, we propose two such strategies that reduce memory energy consumption and yet guarantee realtime memory performance. One provides significant energy savings without impacting the guaranteed bandwidth and latency bounds. The other provides higher energy savings with marginally increased latency bounds, while still preserving the guaranteed bandwidth provided by real-time memory controllers. We also present an algorithm to select the most energy-efficient power-down mode at run-time. We experimentally evaluate the two strategies at run-time by executing four media applications concurrently on a real-time MPSoC platform and show memory energy savings of 42.1% and 51.3% for the two strategies, respectively.