MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
DRAM power management and energy consumption: a critical assessment
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
RAPL: memory power estimation and capping
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
System-level power/performance evaluation of 3D stacked DRAMs for mobile applications
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Understanding the Energy Consumption of Dynamic Random Access Memories
MICRO '43 Proceedings of the 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
Improved Power Modeling of DDR SDRAMs
DSD '11 Proceedings of the 2011 14th Euromicro Conference on Digital System Design
Run-time power-down strategies for real-time SDRAM memory controllers
Proceedings of the 49th Annual Design Automation Conference
CACTI-IO: CACTI with off-chip power-area-timing models
Proceedings of the International Conference on Computer-Aided Design
CACTI-3DD: architecture-level modeling for 3D die-stacked DRAM main memory
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
DRAM selection and configuration for real-time mobile systems
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
An energy efficient DRAM subsystem for 3D integrated SoCs
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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JEDEC recently introduced its new standard for 3D-stacked Wide I/O DRAM memories, which defines their architecture, design, features and timing behavior. With improved performance/power trade-offs over previous generation DRAMs, Wide I/O DRAMs provide an extremely energy-efficient green memory solution required for next-generation embedded and high-performance computing systems. With both industry and academia pushing to evaluate and employ these highly anticipated memories, there is an urgent need for an accurate power model targeting Wide I/O DRAMs that enables their efficient integration and energy management in DRAM stacked SoC architectures. In this paper, we present the first system-level power model of 3D-stacked Wide I/O DRAM memories that is almost as accurate as detailed circuit-level power models of 3D-DRAMs. To verify its accuracy, we experimentally compare its power and energy estimates for different memory workloads and operations against those of a circuit-level 3D-DRAM power model and show less than 2% difference between the two sets of estimates.