Memory bandwidth limitations of future microprocessors
ISCA '96 Proceedings of the 23rd annual international symposium on Computer architecture
Performance isolation: sharing and isolation in shared-memory multiprocessors
Proceedings of the eighth international conference on Architectural support for programming languages and operating systems
Proceedings of the 27th annual international symposium on Computer architecture
Timing Anomalies in Dynamically Scheduled Microprocessors
RTSS '99 Proceedings of the 20th IEEE Real-Time Systems Symposium
WCET Analysis of Probabilistic Hard Real-Time Systems
RTSS '02 Proceedings of the 23rd IEEE Real-Time Systems Symposium
Multiple process execution in cache related preemption delay analysis
Proceedings of the 4th ACM international conference on Embedded software
Safely exploiting multithreaded processors to tolerate memory latency in real-time systems
Proceedings of the 2004 international conference on Compilers, architecture, and synthesis for embedded systems
Memory Controller Optimizations for Web Servers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
DRAMsim: a memory system simulator
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Principles of Timing Anomalies in Superscalar Processors
QSIC '05 Proceedings of the Fifth International Conference on Quality Software
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
High Performance Embedded Computing Handbook
High Performance Embedded Computing Handbook
JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Predator: a predictable SDRAM memory controller
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
RTSS '07 Proceedings of the 28th IEEE International Real-Time Systems Symposium
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Predictable programming on a precision timed architecture
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
CoMPSoC: A template for composable and predictable multi-processor system on chips
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Memory Systems: Cache, DRAM, Disk
Memory Systems: Cache, DRAM, Disk
Hardware support for WCET analysis of hard real-time multicore systems
Proceedings of the 36th annual international symposium on Computer architecture
From a federated to an integrated automotive architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Composable Resource Sharing Based on Latency-Rate Servers
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Making DRAM Refresh Predictable
ECRTS '10 Proceedings of the 2010 22nd Euromicro Conference on Real-Time Systems
Worst case delay analysis for memory interference in multicore systems
Proceedings of the Conference on Design, Automation and Test in Europe
PRET DRAM controller: bank privatization for predictability and temporal isolation
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
An efficient quality-aware memory controller for multimedia platform SoC
IEEE Transactions on Circuits and Systems for Video Technology
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Multicore processors are an effective solution to cope with the performance requirements of real-time embedded systems due to their good performance-per-watt ratio and high performance capabilities. Unfortunately, their use in integrated architectures such as IMA or AUTOSAR is limited by the fact that multicores do not guarantee a time composable behavior for the applications: the WCET of a task depends on inter-task interferences introduced by other tasks running simultaneously. This article focuses on the off-chip memory system: the hardware shared resource with the highest impact on the WCET and hence the main impediment for the use of multicores in integrated architectures. We present an analytical model that computes the worst-case delay, also known as Upper Bound Delay (UBD), that a memory request can suffer due to memory interferences generated by other co-running tasks. By considering the UBD in the WCET analysis, the resulting WCET estimation is independent from the other tasks, hence ensuring the time composability property and enabling the use of multicores in integrated architectures. We propose a memory controller for hard real-time multicores compliant with the analytical model that implements extra hardware features to deal with refresh operations and interferences generated by co-running non hard real-time tasks.