The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Operating systems (3rd ed.): internals and design principles
Operating systems (3rd ed.): internals and design principles
The Ravenscar tasking profile for high integrity real-time programs
Proceedings of the 1998 annual ACM SIGAda international conference on Ada
Modern Operating Systems
Real-Time Systems: Design Principles for Distributed Embedded Applications
Real-Time Systems: Design Principles for Distributed Embedded Applications
Java Virtual Machine Specification
Java Virtual Machine Specification
Distributed Shared Memory: Concepts and Systems
IEEE Parallel & Distributed Technology: Systems & Technology
Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Priority Inheritance Spin Locks for Multiprocessor Real-Time Systems
ISPAN '96 Proceedings of the 1996 International Symposium on Parallel Architectures, Algorithms and Networks
A Profile for High-Integrity Real-Time Java Programs
ISORC '01 Proceedings of the Fourth International Symposium on Object-Oriented Real-Time Distributed Computing
Power Efficient Processor Architecture and The Cell Processor
HPCA '05 Proceedings of the 11th International Symposium on High-Performance Computer Architecture
A time predictable Java processor
Proceedings of the conference on Design, automation and test in Europe: Proceedings
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
WCET analysis for a Java processor
JTRES '06 Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems
Computer Architecture, Fourth Edition: A Quantitative Approach
Computer Architecture, Fourth Edition: A Quantitative Approach
A Profile for Safety Critical Java
ISORC '07 Proceedings of the 10th IEEE International Symposium on Object and Component-Oriented Real-Time Distributed Computing
The coming wave of multithreaded chip multiprocessors
International Journal of Parallel Programming
A Java processor architecture for embedded real-time systems
Journal of Systems Architecture: the EUROMICRO Journal
Static deadlock detection for java libraries
ECOOP'05 Proceedings of the 19th European conference on Object-Oriented Programming
JEOPARD: Java environment for parallel real-time development
JTRES '08 Proceedings of the 6th international workshop on Java technologies for real-time and embedded systems
Decoupled root scanning in multi-processor systems
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
Industry use cases for the Java environment for parallel realtime development
Proceedings of the 9th International Workshop on Java Technologies for Real-Time and Embedded Systems
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
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This paper describes the first steps towards a Java multiprocessor system on a single chip for embedded systems. The chip multiprocessing (CMP) system consists of a homogeneous set of processing elements and a shared memory. Each processor core is based on the Java Optimized Processor (JOP). A major challenge in CMP is the shared memory access of multiple CPUs. The proposed memory arbiter resolves possible emerging conflicts of parallel accesses to the shared memory using a fixed priority scheme. Furthermore, the paper describes the boot-up of the CMP. We verify the proposed CMP architecture by the implementation of the prototype called JopCMP. JopCMP consists of multiple JOPs and a shared memory. Finally yet importantly, the first implementation of the CMP composed of two/three JOPs in an FPGA enables us to present a comparison of the performance between a single-core JOP and the CMP version by running real applications.