JTRES '07 Proceedings of the 5th international workshop on Java technologies for real-time and embedded systems
Multiprocessors and the Real-Time Specification for Java
ISORC '08 Proceedings of the 2008 11th IEEE Symposium on Object Oriented Real-Time Distributed Computing
Limits of parallel marking garbage collection
Proceedings of the 7th international symposium on Memory management
Enhancing the platform independence of the real-time specification for Java
Proceedings of the 7th International Workshop on Java Technologies for Real-Time and Embedded Systems
Educational case studies with an open source embedded real-time Java processor
WESE '09 Proceedings of the 2009 Workshop on Embedded Systems Education
A real-time Java chip-multiprocessor
ACM Transactions on Embedded Computing Systems (TECS)
A locality model for the real-time specification for Java
Proceedings of the 8th International Workshop on Java Technologies for Real-Time and Embedded Systems
Euro-Par'10 Proceedings of the 16th international Euro-Par conference on Parallel processing: Part II
A framework accommodating categorized multiprocessor real-time scheduling in the RTSJ
Proceedings of the 10th International Workshop on Java Technologies for Real-time and Embedded Systems
Hi-index | 0.00 |
Multicore systems have become standard for desktop computers today and current operating systems and software development tools provide straightforward means to use the additional computing power. However, a more fundamental change in the design and development of software is required to fully exploit the power of multicore systems. Furthermore, the fast growing market of embedded systems is currently largely unaffected by the introduction of multicore systems. This will change quickly in the future, which will mean that there will be a demand on efficient development of reliable embedded software that can give real-time guarantees and exploit the available power on multicore systems. The JEOPARD project addresses this demand by developing software tools to exploit multicore power while ensuring correctness and predictable timing.