Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
QoS policies and architecture for cache/memory in CMP platforms
Proceedings of the 2007 ACM SIGMETRICS international conference on Measurement and modeling of computer systems
A high-end real-time digital film processing reconfigurable platform
EURASIP Journal on Embedded Systems
An approach for adaptive DRAM temperature and power management
Proceedings of the 22nd annual international conference on Supercomputing
Efficient Memory Utilization for High-Speed FPGA-Based Hardware Emulators with SDRAMs
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Rate-based QoS techniques for cache/memory in CMP platforms
Proceedings of the 23rd international conference on Supercomputing
Application development with the FlexWAFE real-time stream processing architecture for FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS)
An approach for adaptive DRAM temperature and power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mapping of a film grain removal algorithm to a heterogeneous reconfigurable architecture
Proceedings of the Conference on Design, Automation and Test in Europe
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A bursty multi-port memory controller with quality-of-service guarantees
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Hierarchical memory scheduling for multimedia MPSoCs
Proceedings of the International Conference on Computer-Aided Design
Credit borrow and repay: sharing DRAM with minimum latency and bandwidth guarantees
Proceedings of the International Conference on Computer-Aided Design
PARDIS: a programmable memory controller for the DDRx interfacing standards
Proceedings of the 39th Annual International Symposium on Computer Architecture
A distributed interleaving scheme for efficient access to WideIO DRAM memory
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions
ACM Transactions on Embedded Computing Systems (TECS) - Special section on ESTIMedia'12, LCTES'11, rigorous embedded systems design, and multiprocessor system-on-chip for cyber-physical systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A programmable memory controller for the DDRx interfacing standards
ACM Transactions on Computer Systems (TOCS)
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The ongoing advancements in VLSI technology allow system-on-a-chip (SoC) design to integrate heterogeneous control and computing functions into a single chip. On the other hand, the pressures of area and cost lead to the requirement for a single, shared off-chip DRAM memory subsystem. To satisfy different memory access requirements for latency and bandwidth of these heterogeneous functions to this kind of DRAM memory subsystem, a quality-aware memory controller is important. This paper presents an efficient multilayer, quality-aware memory controller that contains well-partitioned functionality layers to achieve high DRAM utilization while still meet different requirements for bandwidth and latency. Layer 0, also called memory interface socket, is a configurable, programmable, and high-efficient SDRAM controller for designers to rapidly integrate SDRAM subsystem into their designs. Together with Layer 1 quality-aware scheduler, the memory controller also has the capability to provide quality-of-service guarantees including minimum access latencies and fine-grained bandwidth allocation for heterogeneous control and computing functional units in SoC designs. Moreover, Layer 2 built-in address generator designed for multimedia processing units can effectively reduce the address bus traffic and therefore further increase the efficiency of on-chip communication. Experimental results of a digital set-top-box emulation system show that the access latency of the latency-sensitive data flows can be effectively reduced by 37%-65% and the memory bandwidths can be precisely allocated to bandwidth-sensitive data flows with a high degree of control.