Hierarchical memory scheduling for multimedia MPSoCs

Authors:
Ye-Jyun Lin;Chia-Lin Yang;Tay-Jyi Lin;Jiao-Wei Huang;Naehyuck Chang
Affiliations:
National Taiwan University, Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Chung Cheng University, Chiayi, Taiwan;National Taiwan University, Taipei, Taiwan;Seoul National University, Seoul, Korea
Venue:
Proceedings of the International Conference on Computer-Aided Design
Year:
2010

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Abstract

Optimizing memory system performance is critical for delivering high system performance for multimedia applications since they are usually memory intensive. As the number of IP cores in a multimedia MPSoC (Multi-Processor System-on-Chip) continues to increase, system performance will be eventually limited by the memory system. In this paper, we tackle the memory performance issue of multimedida MPSoCs through intelligent memory access scheduling. We observe that since memory resources are shared by all processing elements in an MPSoC, interferences among requests from different IP cores cause not only delay in memory accesses but also unfair DRAM accesses among IPs. Traditional memory scheduling policies that only emphasize on maximizing memory system throughput do not take into account these interferences. Therefore, in this paper, we propose a hierarchical memory scheduling policy to minimize interferences among requests. The experimental results show that the proposed scheduling policy improves system throughput by 21% compared to FR-FCFS (first-ready first-come-first-serve) on an MPSoC for mobile phones with QoS guarantee.