High performance memory mode control for HDTV decoders

Authors:
Seong-II Park;Yongseok Yi;In-Cheol Park
Affiliations:
Div. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Daejeon, South Korea;-;-
Venue:
IEEE Transactions on Consumer Electronics
Year:
2003

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Abstract

To increase the bandwidth of synchronous memories that are widely adopted for HDTV decoder systems, a predictive mode control scheme is proposed in this paper. Memory latency and energy consumption can be reduced by effectively managing the states of banks. The local access history of each bank is considered to predict the memory code. In a HDTV decoder system, experimental results show that the proposed scheme reduces the memory latency and the energy consumption by 18.8% and 23.3%, respectively, over the conventional scheme that always keeps the memory in idle state. Hardware architecture and its VLSI implementation are also presented.