DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Hardware emulation for functional verification of K5
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Proceedings of the 27th annual international symposium on Computer architecture
FPGA prototyping of a RISC processor core for embedded applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Impulse: Building a Smarter Memory Controller
HPCA '99 Proceedings of the 5th International Symposium on High Performance Computer Architecture
Proceedings of the 41st annual Design Automation Conference
An SoC design methodology using FPGAs and embedded microprocessors
Proceedings of the 41st annual Design Automation Conference
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An efficient quality-aware memory controller for multimedia platform SoC
IEEE Transactions on Circuits and Systems for Video Technology
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FPGA-based hardware emulators are often used for the verification of LSI functions. They generally have dedicated external memories, such as SDRAMs, to compensate for the lack of memory capacity in FPGAs. In such a case, access between the FPGAs and the dedicated external memory may represent a major bottleneck with respect to emulation speed since the dedicated external memory may have to emulate a large number of memory blocks. In this paper, we propose three methods, “Dynamic Clock Control (DCC),” “Memory Mapping Optimization (MMO),” and “Efficient Access Scheduling (EAS),” to avoid this bottleneck. DCC controls an emulation clock dynamically in accord with the number of memory accesses within one emulation clock cycle. EAS optimizes the ordering of memory access to the dedicated external memory, and MMO optimizes the arrangement of the dedicated external memory addresses to which respective memories will be emulated. With them, emulation speed can be made 29.0 times faster, as evaluated in actual LSI emulations.