Proceedings of the 27th annual international symposium on Computer architecture
Dynamic Access Ordering for Streamed Computations
IEEE Transactions on Computers
Adaptive History-Based Memory Schedulers
Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
A Real-Time Streaming Memory Controller
Proceedings of the conference on Design, Automation and Test in Europe - Volume 3
Pin: building customized program analysis tools with dynamic instrumentation
Proceedings of the 2005 ACM SIGPLAN conference on Programming language design and implementation
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
Proceedings of the 42nd annual Design Automation Conference
DRAMsim: a memory system simulator
ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Credit borrow and repay: sharing DRAM with minimum latency and bandwidth guarantees
Proceedings of the International Conference on Computer-Aided Design
An efficient quality-aware memory controller for multimedia platform SoC
IEEE Transactions on Circuits and Systems for Video Technology
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)
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Embedded multimedia system-on-chips place an increasing demand on multiport memory controllers (MPMCs) for higher memory system performance and energy efficiency, in addition to satisfying various types of quality-of-service requirements, such as minimum latency and bandwidth guarantees. While previous works have attempted to target different aspects of the MPMC design challenges, none has succeeded in addressing all these problems simultaneously. In this paper, we propose a new approach that can provide, not only minimum latency and bandwidth guarantees, but also higher efficiency in utilization of physical DRAM bandwidth and dynamic bandwidth made available by underutilized ports. Experimental results show that, on typical multimedia workloads, our approach improves the effective DRAM bandwidth and energy efficiency by as much as 1.9x and 1.49x, respectively. In addition, the response latency for latency-sensitive port is improved by more than 10X, while preserving bandwidth guarantee for all ports.