Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements

  • Authors:
  • Sven Heithecker;Rolf Ernst

  • Affiliations:
  • Technical University of Braunschweig;Technical University of Braunschweig

  • Venue:
  • Proceedings of the 42nd annual Design Automation Conference
  • Year:
  • 2005

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Abstract

Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multistream access with different QoS requirements is involved. In [8], a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard realtime constraints for periodic video signals and hard real-time bursty accesses for video coprocessors was described. To handle these contradictory QoS requirements at high system performance, a combination of a 2-stage scheduling algorithm and static priorities were used. This paper describes an additional flow control which enhances the overall performance. Experiments with an FPGA based high-end video platform demonstrate the superiority of this architecture.