An extendible approach for analyzing fixed priority hard real-time tasks
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Application-specific workload shaping in multimedia-enabled personal mobile devices
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NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
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An SDRAM-aware router for networks-on-chip
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CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Credit borrow and repay: sharing DRAM with minimum latency and bandwidth guarantees
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Proceedings of the Conference on Design, Automation and Test in Europe
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DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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Today high-end video and multimedia processing applications require huge amounts of memory. For cost reasons, the usage of conventional dynamic RAM (SDRAM) is preferred. However, SDRAM access optimization is a complex task, especially if multistream access with different QoS requirements is involved. In [8], a multi-stream DDR-SDRAM controller IP covering combinations of low latency requirements for processor cache access, hard realtime constraints for periodic video signals and hard real-time bursty accesses for video coprocessors was described. To handle these contradictory QoS requirements at high system performance, a combination of a 2-stage scheduling algorithm and static priorities were used. This paper describes an additional flow control which enhances the overall performance. Experiments with an FPGA based high-end video platform demonstrate the superiority of this architecture.