Viper: A Multiprocessor SOC for Advanced Set-Top Box and Digital TV Systems
IEEE Design & Test
Real-Time Motion Estimation and Visualization on Graphics Cards
VIS '04 Proceedings of the conference on Visualization '04
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
Proceedings of the 42nd annual Design Automation Conference
An Image Processor for Digital Film
ASAP '05 Proceedings of the 2005 IEEE International Conference on Application-Specific Systems, Architecture Processors
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Introduction to the cell multiprocessor
IBM Journal of Research and Development - POWER5 and packaging
A high-end real-time digital film processing reconfigurable platform
EURASIP Journal on Embedded Systems
Application development with the FlexWAFE real-time stream processing architecture for FPGAs
ACM Transactions on Embedded Computing Systems (TECS)
An algorithm-architecture co-design framework for gridding reconstruction using FPGAs
Proceedings of the 48th Design Automation Conference
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Digital film processing is characterized by a resolution of at least 2K (2048x1536 pixels per frame at 30 bit/pixel and 24 pictures/s, data rate of 2.2 Gbit/s); higher resolutions of 4K (8.8 Gbit/s) and even 8K (35.2 Gbit/s) are on their way. Real-time processing at this data rate is beyond the scope of today's standard and DSP processors, and ASICs are not economically viable due to the small market volume. As an answer to these challenges, an FPGA-based approach was followed in the FlexFilm project. The multi-board, multi-FPGA hardware/software architecture is based on Xilink Virtex-II Pro FPGAs which contain the reconfigurable image stream processing data path, large external SDRAM memories for multiple frame storage, and a PCI Express communication backbone network. Different applications are supported on a single hardware platform by using different FPGA configurations. This paper will focus on the FlexWAFE framework, a component library consisting of parameterizable modules for real-time stream processing including memory and communication controllers. Some of the library blocks' parameters are set at synthesis time via VHDL generics, while others are run-time configurable. This combination allows some flexibility without sacrificing FPGA area or speed.