Access pattern based local memory customization for low power embedded systems
Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
APEX: access pattern based memory architecture exploration
Proceedings of the 14th international symposium on Systems synthesis
Functional abstraction driven design space exploration of heterogeneous programmable architectures
Proceedings of the 14th international symposium on Systems synthesis
Access pattern-based memory and connectivity architecture exploration
ACM Transactions on Embedded Computing Systems (TECS)
Memory Architectures for Embedded Systems-On-Chip
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Modeling and validation of pipeline specifications
ACM Transactions on Embedded Computing Systems (TECS)
Processor-memory coexploration using an architecture description language
ACM Transactions on Embedded Computing Systems (TECS)
Processor/Memory Co-Exploration on Multiple Abstraction Levels
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements
Proceedings of the 42nd annual Design Automation Conference
Retargetable generation of TLM bus interfaces for MP-SoC platforms
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Processor Description Languages
Processor Description Languages
Cycle count accurate memory modeling in system level design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
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Memory represents a major bottleneck in modern embedded systems. Traditionally, memory organizations for programmable systems assumed a fixed cache hierarchy. With the widening processor-memory gap, more aggressive memory technologies and organizations have appeared, allowing customization of a heterogeneous memory architecture tuned for the application. However, such a processor-memory co-exploration approach critically needs the ability to explicitly capture heterogeneous memory architectures. We present in this paper a language-based approach to explicitly capture the memory subsystem configuration, and perform exploration of the memory architecture to trade-off cost versus performance. We present a set of experiments using our Memory-Aware Architectural Description Language to drive the exploration of the memory subsystem for the TIC6211 processor architecture, demonstrating a range of cost and performance attributes.