Cycle count accurate memory modeling in system level design

Authors:
Yi-Len Lo;Mao-Lin Li;Ren-Song Tsay
Affiliations:
National Tsing-Hua University, Taiwan, Hsinchu, Taiwan Roc;National Tsing-Hua University, Taiwan, Hsinchu, Taiwan Roc;National Tsing-Hua University, Taiwan, Hsinchu, Taiwan Roc
Venue:
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Year:
2009

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Abstract

In this paper, we propose an effective automatic generation approach for a Cycle-Count Accurate Memory Model (CCAMM) from the Clocked Finite State Machine (CFSM) of the Cycle Accurate Memory Model (CAMM). Since memory accesses are gradually dominating system activities, a correct and efficient memory timing model is essential to system-level simulation. In general, a CCAMM provides sufficient timing accuracy with low simulation overhead, and hence is preferred over the Simple Fixed Delay Model (SFDM), which has low accuracy, or the CAMM, which has low performance. Our proposed approach can systematically generate the CCAMM and guarantee correctness. The experimental results show that the generated model is as accurate as the Register Transfer Level (RTL) model while running 100X faster.