Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Formal performance evaluation of AMBA-based system-on-chip designs
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Model-driven validation of SystemC designs
EURASIP Journal on Embedded Systems - C-Based Design of Heterogeneous Embedded Systems
MC-Sim: an efficient simulation tool for MPSoC designs
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Cycle count accurate memory modeling in system level design
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
MVTsim: software simulator for multicore on chip parallel computer architectures
CompSysTech '09 Proceedings of the International Conference on Computer Systems and Technologies and Workshop for PhD Students in Computing
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform
Proceedings of the Conference on Design, Automation and Test in Europe
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This paper presents a simulation platform for architecture exploration of bus based heterogeneous multi-processor system-on chips (MPSoC) -- moviSim. The tradeoff between accurate simulation results and simulation time has been obtained by the cycle-count-accurate approach. Its main attributes are: flexibility, integration with the targeted tool chain and increased tracing and analysis capability. The wide range of implemented metrics (program execution time, executed instructions, stalled cycles, bus logging, register and memory port detection, power consumption, function, data and code line profiling, cache metrics (miss/hit ratio, etc), number of memory/subsystem reads/writes performed by a master) allow enhanced architectural exploration capability for complex MPSoC on which large software applications are running. Due to easy integration with debugging tools, the source code targeting the hardware platform can be easily verified and analyzed with the proposed simulation platform.