Modeling and analysis of the system bus latency on the SoC platform
Proceedings of the 2006 international workshop on System-level interconnect prediction
Quantitative analysis of transaction level models for the AMBA bus
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Architecture Exploration for Performance Improvement of SoC Chip Based on AMBA System
ICCIT '07 Proceedings of the 2007 International Conference on Convergence Information Technology
SystemCoDesigner: automatic design space exploration and rapid prototyping from behavioral models
Proceedings of the 45th annual Design Automation Conference
An Electronic System Level Design and Performance Evaluation for Multimedia Applications
ICESS '08 Proceedings of the 2008 International Conference on Embedded Software and Systems
A cycle-count-accurate simulation platform with enhanced design exploration capability
Proceedings of the 5th International ICST Conference on Simulation Tools and Techniques
Automatic generation of high-speed accurate TLM models for out-of-order pipelined bus
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on ESTIMedia'10
Multi-core system performance prediction and analysis at the ESL
International Journal of Computational Science and Engineering
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The increasing complexity of today's system-on-a-chip (SoC) design is challenging the design engineers to evaluate the system performance and explore the design space. Electronic system-level (ESL) design methodology is of great help for attacking the challenges in recent years. In this paper, we present a system-level architecture refinement flow and implement a dual DSP cores virtual system based-on the highly accurate mixed abstraction-level modeling methodology. The constructed virtual platform can run various multimedia applications and achieve high accuracy. Compared with the traditional RTL simulation, the error rate is less than 5% and the simulation speed is around 100 times faster. Using the architecture refinement flow, the system performance profiling and architecture exploration is also realized for the software and hardware engineers to scrutinize the complicated system.