Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Performance Model for a Prioritized Multiple-Bus Multiprocessor System
IEEE Transactions on Computers
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
A Study on Communication Issues for Systems-on-Chip
Proceedings of the 15th symposium on Integrated circuits and systems design
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
System-on-a-chip for digital still cameras with VGA-size video clip shooting
IEEE Transactions on Consumer Electronics
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
System-level bus-based communication architecture exploration using a pseudoparallel algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An accurate system architecture refinement methodology with mixed abstraction-level virtual platform
Proceedings of the Conference on Design, Automation and Test in Europe
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In the SoC, the system bus makes a bottleneck for data communication in high speed on a chip. In addition, the system allows multiple bus layers for efficient management of the bus resources on a SoC. In this paper, we present a latency model of the shared bus connecting multiple IPs. Using the latency model, we analyzed the latencies of the system bus on a SoC to get a throughput needed for the system. This result is used as a criterion for setting optimal bus architecture for a specific SoC design. We get latencies for examples MPEG and USB 2.0 using the proposed latency model and compare with the simulation result from MaxSim tools. As a result, the accuracy of the latency model for a single layer and multiple layers is over 96% and 85%, respectively.