Bandwidth availability of multiple-bus multiprocessors
IEEE Transactions on Computers
A semi-markov model for the performance of multiple-bus systems
IEEE Transactions on Computers
Analysis of multiple-bus interconnection networks
Journal of Parallel and Distributed Computing
Exact performance estimates for multiprocessor memory and bus interference
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
Communication Performance in Multiple-Bus Systems
IEEE Transactions on Computers
Analysis of prioritized crossbar multiprocessor systems
Journal of Parallel and Distributed Computing
Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Computer Architecture and Parallel Processing
Computer Architecture and Parallel Processing
Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors
IEEE Transactions on Computers
A new performance evaluation approach for system level design space exploration
Proceedings of the 15th international symposium on System Synthesis
High-Speed Image reconstruction based on CBP and Fourier Inversion Methods
HPC-ASIA '97 Proceedings of the High-Performance Computing on the Information Superhighway, HPC-Asia '97
Modeling and analysis of the system bus latency on the SoC platform
Proceedings of the 2006 international workshop on System-level interconnect prediction
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The performance of a shared memory multiprocessor system with a multiple-bus interconnection network is studied in this paper. The effect of bus and memory contention is modeled using a probabilistic model and a closed form solution for the acceptance probability of each processor is presented. It is assumed that each processor in the system has a distinct priority assigned to it and that arbitration is based on priority. Whenever a request from a processor is rejected due to bus or memory conflicts, the request is resubmitted until granted. Based on the model, individual processor acceptance probabilities are first estimated, from which the effective memory bandwidth is computed. The accuracy of the analytical model is verified based on simulation results. Results from the model are compared against other approximate models previously reported in literature. It is observed that the inaccuracy of the model measured in terms of error from simulation results is less than that in previously reported studies.