Performance Model for a Prioritized Multiple-Bus Multiprocessor System
IEEE Transactions on Computers
HLS: combining statistical and symbolic simulation to guide microprocessor designs
Proceedings of the 27th annual international symposium on Computer architecture
On Performance Prediction of Parallel Computations with Precedent Constraints
IEEE Transactions on Parallel and Distributed Systems
A Framework for Statistical Modeling of Superscalar Processor Performance
HPCA '97 Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture
System-Level Performance Estimation Strategy for Sw and Hw
ICCD '98 Proceedings of the International Conference on Computer Design
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Application specific systems have potential for customization of design with a view to achieve a better cost-performance-power trade-off. Such customization requires extensive design space exploration. In this paper, we introduce a performance evaluation methodology for system-level design exploration that is much faster than traditional cycle-accurate simulation. The trade off is between accuracy and simulation speed. The methodology is based on probabilistic modeling of system components customized with application behavior. Performance numbers are generated by simulating these models. We have implemented our models using SystemC and validated these for uni processor as well as multiprocessor systems against various benchmarks.