Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
Bandwidth availability of multiple-bus multiprocessors
IEEE Transactions on Computers
A semi-markov model for the performance of multiple-bus systems
IEEE Transactions on Computers
Analysis of a class of cluster-based multiprocessor systems
Information Sciences: an International Journal
Hypernet: A communication-efficient architecture for constructing massively parallel computers
IEEE Transactions on Computers
Effective Memory Bandwidth and Processor Blocking Probability in Multiple-Bus Systems
IEEE Transactions on Computers
The Balance Multiprocessor System
IEEE Micro
Communication Performance in Multiple-Bus Systems
IEEE Transactions on Computers
Hierarchical Interconnection Networks for Multicomputer Systems
IEEE Transactions on Computers
Digital bus handbook
Analysis of Packet-Switched Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Performance Analysis of Multiple Bus Interconnection Networks with Hierarchical Requesting Model
IEEE Transactions on Computers
Fundamentals of Performance Modeling
Fundamentals of Performance Modeling
Performance Analysis of a Generalized Class of M-Level Hierarchical Multiprocessor Systems
IEEE Transactions on Parallel and Distributed Systems
Performance Model for a Prioritized Multiple-Bus Multiprocessor System
IEEE Transactions on Computers
Performance Modeling of Hierarchical Crossbar-Based Multicomputer Systems
IEEE Transactions on Computers
CPMBK: An improved cluster-based interconnection network
International Journal of Computer Applications in Technology
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A multiple bus system provides more bandwidth and a high degree of fault tolerance than a single bus system. But such a system becomes very expensive for a large number of processors and memory modules, due to the requirement of too many connections (switches). Lang (1983) proposed a different bus-based system, known as the partial multiple bus system, which requires a lower number of connections than a multiple bus system, but with a slight degradation in system performance. This paper presents a new type of bus-based system, called the multilevel bus system. Such a bus architecture can be used to design hierarchical multiprocessors. This bus-based system requires significantly less connections than multiple and partial multiple bus systems. This system is very cost-effective, as compared to multiple and partial multiple bus systems, when there exists some locality in the computations. Analytical and simulation models have been developed to determine the performance of both synchronous and asynchronous multilevel bus systems. The results obtained from the analysis show that a multilevel bus system performs fairly close to other bus-based systems for the hierarchical reference (HR) model. In the HR model, a processor accesses its nearest memory modules more frequently than other memory modules.