Quantitative system performance: computer system analysis using queueing network models
Quantitative system performance: computer system analysis using queueing network models
Analyzing multiple register sets
ISCA '85 Proceedings of the 12th annual international symposium on Computer architecture
A partial-multiple-bus computer structure with improved cost effectiveness
ISCA '88 Proceedings of the 15th Annual International Symposium on Computer architecture
Analysis of Packet-Switched Multiple-Bus Multiprocessor Systems
IEEE Transactions on Computers
Performance Model for a Prioritized Multiple-Bus Multiprocessor System
IEEE Transactions on Computers
Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors
IEEE Transactions on Computers
Multi-layer bus minimization for SoC
Journal of Systems and Software
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A simple queueing model is presented for studying the effect of multiple-bus interconnection networks on the performance of asynchronous multiprocessor systems. The proposed model is suitable for systems in which each processor has a local memory and is thus able to continue processing while waiting for a response from the global memory. An approximate, closed-form solution is given that is simple and easy to use for any number of processors, buses, or memory modules and for arbitrary memory block size. The model is used to study the access time of the global memory as a function of the number of buses for different local-memory/global-memory traffic rates.