Generation of interconnect topologies for communication synthesis
Proceedings of the conference on Design, automation and test in Europe
Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
A survey of techniques for energy efficient on-chip communication
Proceedings of the 40th annual Design Automation Conference
Transaction level modeling: an overview
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Transaction level modeling: flows and use models
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Transaction-Level Models for AMBA Bus Architecture Using SystemC 2.0
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2
SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and analysis of the system bus latency on the SoC platform
Proceedings of the 2006 international workshop on System-level interconnect prediction
GreenBus: a generic interconnect fabric for transaction level modelling
Proceedings of the 43rd annual Design Automation Conference
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Communication Architecture Synthesis of Cascaded Bus Matrix
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Industrial IP integration flows based on IP-XACT™ standards
Proceedings of the conference on Design, automation and test in Europe
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Automated bus generation for multiprocessor SoC design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EPIDETOX: an ESL platform for integrated circuit design and tool exploration
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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Growing complexity in system-on-a-chip (SoC) design demands effective approaches to explore various architectures quickly for the target applications. With the common use of intellectual properties (IPs) in SoC and the large amount of data interchanges among IPs, communication architecture significantly affects the system in terms of power and performance. Therefore, designers should carefully plan the communication architecture to meet the power and performance requirements. While repeatedly performing a power optimization under a performance constraint approach N times seems practical for the power and performance coexploration, the time required to explore such solutions inevitably increases, since there are numerous performance constraints. This paper presents a pseudoparallel method for bus architecture exploration at the system level (PBAES) to speedup the power and performance of coexploration time. PBAES can intelligently search interesting portions of the design space to enhance the efficiency of coexploration, and share the candidate solutions of each to achieve a more rapid overall exploration. The experimental results indicate that PBAES is 1.6× to 14× faster than an approach without the pseudoparallel method with a generated architecture of similar quality.