Generation of interconnect topologies for communication synthesis

Authors:
M. Gasteier;M. Münch;M. Glesner
Affiliations:
Darmstadt Universityof Technology, Institute of Microelectronic Systems, Karlstraβe 15, D-64283 Darmstadt, Germany;University of Kaiserslautern, Institute of Microelectronic Systems, Erwin-Schrödinger-Straβe, D-67663 Kaiserslautern, Germany;Darmstadt Universityof Technology, Institute of Microelectronic Systems, Karlstraβe 15, D-64283 Darmstadt, Germany
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
1998

Citing 6
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Abstract

One of the key problems in hardware/software co-design is communication synthesis which determines the amount and type of interconnect between the hardware components of a digital system. To do so, communication synthesis derives a communication topology to determine which components are to be connected to a common communication channel in the final hardware implementation. In this paper, we present a novel approach to cluster processes to share a communication channel. An iterative graph-based clustering algorithm is driven by a heterogeneous cost function which takes into account bit widths, the probability of access collisions on the channels, cost for arbitration logic as well as the availability of interface resources on the hardware components to trade-off cost against performance in a most optimum fashion. The key aspects of the approach are demonstrated on a small example.