Co-simulation and communication synthesis approach for intellectual properties based SoCs

  • Authors:

  • Mehrez Marzougui;Mohamed Abid;Adel Baganne;Rached Tourki

  • Affiliations:

  • Electronics and Micro-Electronics Laboratory, Faculty of Sciences at Monastir, Monastir 5000, Tunisia;Electronics and Micro-Electronics Laboratory, Faculty of Sciences at Monastir, Monastir 5000, Tunisia;LESTER, UBS Research Center, St-Maudé Av., BP 92116, 56321 Lorient cedex, France;Electronics and Micro-Electronics Laboratory, Faculty of Sciences at Monastir, Monastir 5000, Tunisia

  • Venue:
  • Computers and Electrical Engineering
  • Year:
  • 2004

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Abstract

This paper presents an approach to integrate intellectual properties (IPs) based systems on chip (SoCs). The aim is to synthesize communication units using co-simulation environment and a stochastic process. The proposed approach allows to bound communication memories for different loading rates of the master processor. According to the chosen communication unit while interconnecting IPs components, this approach also allows to refine communication structures in order to lead to a model easily mappable onto the target architecture. The approach has been experimented and validated through a detailed case study concerning the verification and the integration of the discrete and direct wavelet transform (DDWT) IP in a mixed hardware/software architecture. Software partitions are executed on the ARM7 processor and hardware partitions are executed on the ModelSim simulator. The used co-simulation tool is Seamless CVE(TM) of Mentor Graphics. A library of adaptation protocols of IP blocs to the environment as well as a set of standard communication units (RAM, DPRAM, FIFOs) have been also developed and used.