IEEE Transactions on Software Engineering - Special issue on formal methods in software practice
What's between simulation and formal verification? (extended abstract)
DAC '98 Proceedings of the 35th annual Design Automation Conference
Simulation-guided property checking based on a multi-valued AR-automata
Proceedings of the conference on Design, automation and test in Europe
Validating the intel pentium 4 microprocessor
Proceedings of the 38th annual Design Automation Conference
Symbolic Model Checking
Smart simulation using collaborative formal and simulation engines
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
FoCs: Automatic Generation of Simulation Checkers from Formal Specifications
CAV '00 Proceedings of the 12th International Conference on Computer Aided Verification
Verification of Transaction-Level SystemC models using RTL Testbenches
MEMOCODE '03 Proceedings of the First ACM and IEEE International Conference on Formal Methods and Models for Co-Design
Assertion-Based Design
Combining System Level Modeling with Assertion Based Verification
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
Transaction-Level Modeling with Systemc: Tlm Concepts and Applications for Embedded Systems
An automatic ABV methodology enabling PSL assertions across SLD flow for SOCs modeled in SystemC
Computers and Electrical Engineering
Co-simulation and communication synthesis approach for intellectual properties based SoCs
Computers and Electrical Engineering
A systematic approach to configurable functional verification of HW IP blocks at transaction level
Computers and Electrical Engineering
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In complex System on Chips (SoCs), system level platforms are built around a set of IPs including processor cores, memories and dedicated hardware (FPGA, ASIC). The better for modeling is using a single system level language during implementation. However, as IPs are in different languages, there is a need to several adaptations and conversion processes, hence making the platforms un-optimized. In this paper we fit the optimization problems by enhancing performances of SystemC SoC platforms according to a treble: productivity, simulation speed and improved verification. We enabled the two first using ST Microelectronics mature techniques and the third with a novel assertion-based verification that we proposed in this paper. As experimentation we used realistic IPs from ST Microelectronics and ARM in order to build the SoC platforms. Among these IPs, some are modeled in VHDL, some other are in Verilog and the rest are in SystemC.