Modeling and analysis of the system bus latency on the SoC platform
Proceedings of the 2006 international workshop on System-level interconnect prediction
On-chip bus modeling for power and performance estimation
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
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An advanced, compact and low-power system-on-a-chip has been developed that permits a single chip to perform all of the necessary functions for a DSC (digital still camera). Quality VGA-size motion pictures can be recorded at a rate of 30 fps