Multiprocessor SoC Platforms: A Component-Based Design Approach
IEEE Design & Test
A Comparison of Five Different Multiprocessor SoC Bus Architectures
DSD '01 Proceedings of the Euromicro Symposium on Digital Systems Design
Power analysis of system-level on-chip communication architectures
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
System-on-a-chip for digital still cameras with VGA-size video clip shooting
IEEE Transactions on Consumer Electronics
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This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design.