The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The SimpleScalar tool set, version 2.0
ACM SIGARCH Computer Architecture News
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architectural power optimization by bus splitting
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Multiprocessor enhancements of the SimpleScalar tool set
ACM SIGARCH Computer Architecture News
LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Genetic algorithms for graph partitioning and incremental graph partitioning
Proceedings of the 1994 ACM/IEEE conference on Supercomputing
AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Design space exploration for optimizing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
The SegBus platform - architecture and communication mechanisms
Journal of Systems Architecture: the EUROMICRO Journal
Local search: is brute-force avoidable?
IJCAI'09 Proceedings of the 21st international jont conference on Artifical intelligence
On-chip bus modeling for power and performance estimation
SAMOS'07 Proceedings of the 7th international conference on Embedded computer systems: architectures, modeling, and simulation
Efficient exploration of bus-based system-on-chip architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we provide a methodology to perform both bus partitioning and bus frequency assignment to each of the bus segment simultaneously while optimizing both power consumption and performance of the system. We use a genetic algorithm and design an appropriate cost function which optimizes the solution on the basis of its power consumption and performance. The evaluation of our approach using a set of multiprocessor applications show that an average reduction of the energy consumption by 60% over a single shared bus architecture. Our results also show that it is beneficial to simultaneously assign bus frequencies and performing bus partitioning instead of performing them sequentially.