Segmented bus design for low-power systems

Authors:
J. Y. Chen;W. B. Jone;J. S. Wang;H.-I. Lu;T. F. Chen
Affiliations:
National Chung-Cheng Univ., Chiayi, Taiwan, R.O.C;National Chung-Cheng Univ., Chiayi, Taiwan, R.O.C;National Chung-Cheng Univ., Chiayi, Taiwan, R.O.C;National Chung-Cheng Univ., Chiayi, Taiwan, R.O.C;National Chung-Cheng Univ., Chiayi, Taiwan, R.O.C
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
1999

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Abstract

This paper proposes a bus-segmentation method that efficiently reduces the switched capacitance on the bus. The power consumed by the bus can, therefore, be substantially reduced. The basic idea of bus segmentation is to partition the bus into several bus segments separated by pass transistors. Highly communicating devices are located to adjacent bus segments, thus, most data communication can be achieved by switching a small portion of the bus segments. As a result, power consumption and critical path delay are both reduced. Experimental results obtained by simulating a delay model and a power model demonstrate that the proposed segmented bus system reduces bus power by about 60%-70% and improves critical bus delay by about 10%-30%.