Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
A force-directed macro-cell placer
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Fixed-Outline Floorplanning through Better Local Search
ICCD '01 Proceedings of the International Conference on Computer Design: VLSI in Computers & Processors
A Trade-off Oriented Placement Tool
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture
Proceedings of the 2006 international workshop on System-level interconnect prediction
Physical design implementation of segmented buses to reduce communication energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
VLSI module placement based on rectangle-packing by the sequence-pair
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Control for power gating of wires
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The increasing gap between design productivity and chip complexity and the emerging systems-on-chip (SoCs) architectural template have led to the wide utilization of reusable hard intellectual property (IP) cores. Macro block-based physical design implementation needs to find a well-balanced solution among chip area, on-chip communication energy, and critical communication path delay. We present in this paper an automated way to implement an energy optimal netlist interconnecting the hard macro blocks using a heavily segmented communication architecture. We explore the entire tradeoff curve among the network energy, chip area, and critical communication path delay at the floorplanning stage based on two real-life application drivers. Large energy gains with small area overheads are illustrated during the floorplanning stage. This tradeoff profile is a good guideline for the SOC designers to choose the optimal solution for their specific systems.