Fibonacci heaps and their uses in improved network optimization algorithms
Journal of the ACM (JACM)
Rotation scheduling: a loop pipelining algorithm
DAC '93 Proceedings of the 30th international Design Automation Conference
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embedded Multiprocessors: Scheduling and Synchronization
Embedded Multiprocessors: Scheduling and Synchronization
Design theory and implementation for low-power segmented bus systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Physical design implementation of segmented buses to reduce communication energy
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Proceedings of the 13th ACM SIGPLAN/SIGBED International Conference on Languages, Compilers, Tools and Theory for Embedded Systems
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Energy efficient and high performance interconnect is critical for multi-core architecture. Interconnect with power saving segmented buses satisfies the tight latency and high volumn data transfer needs of applications with large embeded pallelism. This paper analyzes the major energy consumption factors of interconnect with segmented buses from high level synthesis. It presents a computation and inter-core data transfer scheduling algorithm to minimize the interconnect energy consumption by addressing the analyzed factors while exploring an application's maximum parallelism. This paper jointly considers scheduling and interconnect design. It presents an application specific approach to determine the minimum number of segmented buses required and an optimal inter core data transfer schedule which can be used to configure the switches on the segmented buses to avoid bus contention and minimize interconnect energy consumption with a given application. Experimental results show that the proposed scheduling algorithm can reduce interconnect dynamic energy consumption about 71% and static energy consumption about 23% on average compared to the other communication cost conscious scheduling techniques for evaluated high parallelism DSP applications.