Simulated annealing: theory and applications
Simulated annealing: theory and applications
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Low-swing interconnect interface circuits
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Segmented bus design for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 39th annual Design Automation Conference
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
CMOS Circuit Speed and Buffer Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Differential bidirectional transceiver for on-chip long wires
Microelectronics Journal
CMOS linear high performance push amplifier for WiMAX power amplifier
Microelectronics Journal
Interconnect optimization to enhance the performance of subthreshold circuits
Microelectronics Journal
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In this article, two accurate and efficient approaches are proposed to optimize the power and delay of global interconnects in VLSI ICs. We modify the conventional buffer insertion and low swing methods for delay and power optimization of various lengths of the global interconnects. As such, we address non-equidistance buffer insertion (NEBI) and current-mode driver and receiver (CMDR) techniques along with our smart optimization procedure. It is shown that the optimized low swing CMDR technique is efficient for global interconnects of the length equal or longer than 5mm, and the improved buffer insertion technique, NEBI, is a perfect choice for the short global interconnects. Additionally, a random search algorithm known as simulated annealing (SA), improved by an intelligent method using a piecewise linear and exponential cost function, is employed for optimization of the power and delay. To this end, we have implemented a smart CAD tool that works interactively with HSPICE to achieve accurate and reliable design results. For verification purposes, several circuits are designed and simulated in 0.25, 0.18, and 0.13@mm CMOS technologies. The simulation results verify a significant reduction in the power and delay of global interconnects compared to other methods in the literature.