Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Low-power and high-performance techniques in global interconnect signaling
Microelectronics Journal
Low-power current-mode transceiver for on-chip bidirectional buses
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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This work presents a differential bidirectional transceiver (DBT) for on-chip long wires. To enhance operating speed and reduce power consumption, the voltage swing on the wire is reduced using current-mode scheme. Consequently, our design performs higher data rate when wire length is extended. Moreover, adoption of differential scheme with a moderate tradeoff of area effectively lowers power supply noise and common mode noise. The receiver adopts four input differential pairs along with current summation circuit to evaluate small signal differences of every that state resulted from transmitting different data. Simulations using 0.18-@mm device model indicates that the total input to output delay over a 5mm long wire is 0.96ns, with a power consumption of 8.724mW at a speed of 1.2Gbps and a maximum achievable data rate of 1.5Gbps. A test chip is realized and successfully verifies the performance of the transceiver.