Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy

Authors:
Vani Prasad;Madhav P. Desai
Affiliations:
-;-
Venue:
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Year:
2003

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Abstract

We consider the problem of minimizing the delay intransporting a signal across a distance in a VLSI circuit. Theproblem can be restated as a combined buffer insertion,buffer sizing and wire sizing problem. We propose a simplebuffering architecture for this problem and show thatthis architecture achieves a near optimal solution. We alsoderive simple models for a buffered wire which are suitablefor high level design.