Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Interconnect Delay Minimization Using a Novel Pre-Mid-Post Buffer Strategy
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Design and Analysis of Low-Voltage Current-Mode Logic Buffers
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Robust Multi-Level Current-Mode On-Chip Interconnect Signaling in the Presence of Process Variations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Novel Low Power Multilevel Current Mode Interconnect System
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Low-power current-mode transceiver for on-chip bidirectional buses
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
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In this paper we show that current mode signaling system with receivers using inductive input impedance can provide a low power solution to high speed data transmission over long lines. We show that beta multiplier circuits can be designed such that they exhibit inductive input impedance and their use as current mode receivers provides significant enhancement in data rates. Simulation results show that it is possible to transmit data at eight times higher data rates than voltage mode with an one order of magnitude lower power consumption. Even compared to other current mode signaling systems, those using receiver with inductive input impedance show around 50% improvement in data rate at marginally lower power consumption.