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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A quadratic programming approach to simultaneous buffer insertion/sizing and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Interconnect Criticality-Driven Delay Relaxation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper addresses the problem of delay and power minimization in transmitting a signal along a distance in wire segments in field-programmable gate arrays (FPGAs). With the continuous scaling of the IC technology node, while transistors become faster, wires become slower. Delay and power are considered to be the most important issues in designing FPGAs. In FPGAs, crossing signals can exit from the end of wire segments or exit from somewhere before the end point via Early Turns. This paper presents an efficient method for obtaining optimum places for Early Turns, and then reducing two types of delays including the expected delay, and the end-to-end delay. Also by using this method power can be reduced. A method has been proposed to reduce the FPGAs delay and power in wire segmentations by buffer insertion while choosing the best size and place for the buffers. We present a technique to find Early Turn points as proper places for buffer insertion. Simulation results for the 45nm technology node prove that the expected delay of the proposed wire segmentation structure has up to 53% better performance compared with the buffered interconnects constructed with only the end-to-end delay optimization. Also our results show that when the power optimization is performed based on the expected power, the power is improved 46% compared with the case that only the end-to-end power is optimized.