ISPD '99 Proceedings of the 1999 international symposium on Physical design
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Proceedings of the 49th Annual Design Automation Conference
Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires
Microelectronics Journal
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With an ever-increasing portion of the delay in high-speed CMOS chips attributable to the interconnect, interconnect-circuit design automation continues to grow in importance. By transforming the gate and multilayer wire sizing problem into a convex programming problem for the Elmore delay approximation, we demonstrate the efficacy of a sequential quadratic programming (SQP) solution method. For cases where accuracy greater than that provided by the Elmore delay approximation is required, we apply SQP to the gate and wire sizing problem with more accurate delay models. Since efficient calculation of sensitivities is of paramount importance during SQP, we describe an approach for efficient computation of the RC circuit delay sensitivities