Simultaneous driver and wire sizing for performance and power optimization
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
RC interconnect optimization under the Elmore delay model
DAC '94 Proceedings of the 31st annual Design Automation Conference
Exact moment matching model of transmission lines and application to interconnect delay estimation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Optimal wiresizing under the distributed Elmore delay model
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Calculating worst-case gate delays due to dominant capacitance coupling
DAC '97 Proceedings of the 34th annual Design Automation Conference
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Wire sizing as a convex optimization problem: exploring the area-delay tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
The Elmore delay as a bound for RC trees with generalized input signals
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A sequential quadratic programming approach to concurrent gate and wire sizing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
EWA: efficient wiring-sizing algorithm for signal nets and clock nets
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Metrics and bounds for phase delay and signal attenuation in RC(L) clock trees
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Digital Circuit Optimization via Geometric Programming
Operations Research
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There has been substantial work on interconnect sizing algorithms for delay and area optimization in terms of the Elmore delay. Recently, however, signal integrity issues have become of equal or greater importance than delay and area for deep submicron designs. Modeling signal integrity requires more than the Elmore delay approximation, especially when interconnect inductance effects are considered. This paper studies a new interconnect sizing formula冒tion with signal attenuation and transition time constraints that cap冒tures the same global optimality as the Elmore delay based approaches. With the signal attenuation (or the signal transition time) modeled by the second order central moment of the circuit response, we formulate a provably posynomial optimization prob冒lem for RC trees such that the well studied algorithms for geometric programming can be applied with guaranteed convergence to a glo冒bal minima. For RCL cases we demonstrate that this formulation remains convex and posynomial under reasonable conditions. Suffi冒cient conditions are given in terms of the technology parameters and termination conditions.