Analytical delay models for VLSI interconnects under ramp input
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Interconnect layout optimization under higher-order RLC model
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Proceedings of the conference on Design, automation and test in Europe
A graph based algorithm for optimal buffer insertion under accurate delay models
Proceedings of the conference on Design, automation and test in Europe
Hierarchical model order reduction for signal-integrity interconnect synthesis
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
A fast and accurate delay estimation method for buffered interconnects
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Proceedings of the 39th annual Design Automation Conference
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
New Efficient and Accurate Moment Matching Based Model for Crosstalk Estimation in Coupled RC Trees
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Timing modeling and optimization under the transmission line model
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach
Proceedings of the 20th annual conference on Integrated circuits and systems design
Analytical timing model for inductance-dominant interconnect based on traveling wave propagation
Microelectronics Journal
A fast symbolic computation approach to statistical analysis of mesh networks with multiple sources
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
State-space analytical modelling for on-chip coupling effects
ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
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Moment matching methods are widely used in delay estimation of interconnects modeled as transmission line networks. In this paper, we analyze the contribution of a transmission line to the moments of a resistor-transmission line-capacitor (R-T-C) network and provide a method to form a lumped moment matching model of the line. When the transmission lines are replaced by their pth order moment matching models, the network is transformed into a lumped R-L-C network such that these two networks have identical moments up to the order of p for each corresponding output node voltage. We also provide a recursive formula to compute the moments of the R-L-C network so that the moment matching techniques can be efficiently used in the delay estimation.