State-space analytical modelling for on-chip coupling effects

  • Authors:
  • H. J. Kadim

  • Affiliations:
  • School of Engineering, Liverpool JM University, Liverpool, UK

  • Venue:
  • ICC'06 Proceedings of the 10th WSEAS international conference on Circuits
  • Year:
  • 2006

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Abstract

Increasing interconnect-densities and high clock rates give rise to cross-coupling effects between on-chip interconnect wires - thus leading to significant delay and crosstalk noise problems that may affect signal integrity. In this paper, state-space-based analytical modelling expressions to examine the effect of crosstalk noise on circuit parameters are presented.