Zero-skew clock tree construction by simultaneous routing, wire sizing and buffer insertion
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
RC(L) interconnect sizing with second order considerations via posynomial programming
Proceedings of the 2001 international symposium on Physical design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Geometric programming for circuit optimization
Proceedings of the 2005 international symposium on Physical design
Delay and Power Estimation Models of Low-Swing Interconnects for Design Planning
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Clock buffer and wire sizing using sequential programming
Proceedings of the 43rd annual Design Automation Conference
Digital Circuit Optimization via Geometric Programming
Operations Research
The Optimal Architecture Design of Two-Dimension Matrix Multiplication Jumping Systolic Array
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Clock skew minimization in multi-voltage mode designs using adjustable delay buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Revisiting automated physical synthesis of high-performance clock networks
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Smart non-default routing for clock power reduction
Proceedings of the 50th Annual Design Automation Conference
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The wire sizing problem under inequality Elmore delay constraints is known to be posynomial, hence convex under an exponential variable transformation. Due to their efficiency and ease of implementation, one-wire-at-a-time downhill improvement heuristics are often applied to solve such problems. Unfortunately, when there are complex boundary constraints, the solutions from such heuristics can be far away from the global minimum. There are formal methods for solving convex programs, but they are too costly in terms of runtime for some applications. Some optimization techniques can be quite efficient but they solve less desirable formulations, such as minimum weighted sum of area and critical path delays. This paper proposes an efficient wire-sizing algorithm (EWA) that is able to trade solution accuracy for time efficiency while providing an upper bound on the distance from the optimal solution. EWA solves the practical problem of minimizing the total wiring area or the capacitance of an interconnect RC tree subject to hard constraints on the Elmore delay. The implementation is simple and efficiency is comparable to the available heuristics. No restrictions are placed on the circuit or wire widths. Furthermore, it is shown that the optimal wire width assignment for a minimum wiring area objective satisfies all the delay constraints as equalities when minimum wire width constraints are not active. It follows that EWA can be applied for problems with equality delay constraints such as clock trees. Moreover, this and other properties are general enough to permit extensions to higher order delay models and can be used to enhance other optimization methods