RC interconnect optimization under the Elmore delay model

RC interconnect synthesis—a moment fitting approach

ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design

Simultaneous gate and interconnect sizing for circuit-level delay optimization

DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference

Post routing performance optimization via tapered link insertion and wiresizing

EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation

Optimal wire sizing and buffer insertion for low power and a generalized delay model

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

A sequential quadratic programming approach to concurrent gate and wire sizing

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Optimal wiresizing for interconnects with multiple sources

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Post routing performance optimization via multi-link insertion and non-uniform wiresizing

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design

Optimal wiresizing for interconnects with multiple sources

ACM Transactions on Design Automation of Electronic Systems (TODAES)

New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Fast performance-driven optimization for buffered clock trees based on Lagrangian relaxation

DAC '96 Proceedings of the 33rd annual Design Automation Conference

Optimal non-uniform wire-sizing under the Elmore delay model

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

An efficient approach to simultaneous transistor and interconnect sizing

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design

Simultaneous buffer and wire sizing for performance and power optimization

ISLPED '96 Proceedings of the 1996 international symposium on Low power electronics and design

Timing optimization for multi-source nets: characterization and optimal repeater insertion

DAC '97 Proceedings of the 34th annual Design Automation Conference

A new approach to simultaneous buffer insertion and wire sizing

ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design

EWA: exact wiring-sizing algorithm

Proceedings of the 1997 international symposium on Physical design

Closed form solution to simultaneous buffer insertion/sizing and wire sizing

Proceedings of the 1997 international symposium on Physical design

Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

ISPD '99 Proceedings of the 1999 international symposium on Physical design

FAR-DS: full-plane AWE routing with driver sizing

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Equivalent Elmore delay for RLC trees

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

Is wire tapering worthwhile?

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design

RC(L) interconnect sizing with second order considerations via posynomial programming

Proceedings of the 2001 international symposium on Physical design

Optimal spacing and capacitance padding for general clock structures

Proceedings of the 2001 Asia and South Pacific Design Automation Conference

A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design

Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs

VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Wire sizing and spacing for lithographic printability and timing optimization

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Power characteristics of inductive interconnect

IEEE Transactions on Very Large Scale Integration (VLSI) Systems