Post routing performance optimization via tapered link insertion and wiresizing

  • Authors:
  • Tianxiong Xue;Ernest S. Kuh

  • Affiliations:
  • Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA;Department of Electrical Engineering and Computer Sciences, University of California at Berkeley, Berkeley, CA

  • Venue:
  • EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
  • Year:
  • 1995

Quantified Score

Hi-index 0.00

Visualization

Abstract