Utilizing redundancy for timing critical interconnect

Authors:
Shiyan Hu;Qiuyang Li;Jiang Hu;Peng Li
Affiliations:
Department of Electrical and Computer Engineering, Taxas A&M University, College Station, TX;Department of Electrical and Computer Engineering, Taxas A&M University, College Station, TX;Department of Electrical and Computer Engineering, Taxas A&M University, College Station, TX;Department of Electrical and Computer Engineering, Taxas A&M University, College Station, TX
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2007

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Abstract

Conventionally, the topology of signal net routing is almost always restricted to Steiner trees, either unbuffered or buffered. However, introducing redundant paths into the topology (which leads to non-tree) may significantly improve timing performance as well as tolerance to open faults and variations. These advantages are particularly appealing for timing critical net routings in nanoscale VLSI designs where interconnect delay is a performance bottleneck and variation effects are increasingly remarkable. We propose Steiner network construction heuristics which can generate either tree or non-tree with different slack-wirelength tradeoff, and handle both long path and short path constraints. We also propose heuristics for simultaneous Steiner network construction and buffering, which may provide further improvement in slack and resistance to variations. Furthermore, incremental non-tree delay update techniques are developed to facilitate fast Steiner network evaluations. Extensive experiments in different scenarios show that our heuristics usually improve timing slack by hundreds of pico seconds compared to traditional approaches. When process variations are considered, our heuristics can significantly improve timing yield because of nominal slack improvement and delay variability reduction.