Post routing performance optimization via tapered link insertion and wiresizing
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Non-tree routing for reliability and yield improvement
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Yield Improvement by Local Wiring Redundancy
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Considering possible opens in non-tree topology wire delay calculation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Utilizing redundancy for timing critical interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
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For timing-driven or yield-driven designs, non-tree routing has become more and more popular and additional loops provide the redundant paths to protect against the effect of the open defects. Based on the assumption of a single wiring open in a signal net, it is known that the non-tree interconnection of a signal net has no adjacent loop. In this paper, based on the concept of splitting a time-equivalent node or edge in a cyclic connection for timing analysis, a 0-1 integer linear programming(ILP) formulation for resource-constrained timing-driven link insertion is proposed to insert timing-driven links to maximize the reduced delay of the critical path in a rectilinear Steiner tree under a given resource constraint. The experimental results show that our proposed algorithm has the 21.0% and 23.5% reduction of the critical delay on the average for the tested trees in reasonable CPU time under the 10% and 20% resource constraint of the total wirelength, respectively.