Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
A Simple via Duplication Tool for Yield Enhancement
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Physical Design Challenges for Billion Transistor Chips
ICCD '02 Proceedings of the 2002 IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD'02)
Redundant-via enhanced maze routing for yield improvement
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Nontree routing for reliability and yield improvement [IC layout]
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Robust wiring networks for DfY considering timing constraints
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Considering possible opens in non-tree topology wire delay calculation
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Redundant wire insertion for yield improvement
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Resource-constrained timing-driven link insertion for critical delay reduction
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Resource-constrained link insertion for delay reduction
Integration, the VLSI Journal
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Technology migration from 130 nm to 90 nm has resulted in increased yield loss caused by opens in wiring interconnects and vias. Sensitivity to these defects can be significantly reduced through the use of design methodologies that use arbitrary networks with high degrees of redundancy instead of trees for signal wires. In this paper we describe a technique that improves yield by adding via redundancy through the use of local loops. The commonly used practice of inserting a second via adjacent to an existing via can only be applied to a limited number of vias, generates wrong-way wiring, and does not significantly reduce critical area because of the proximity of the two vias. Industry examples are cited to show that use of local loops to create redundancy reduces critical area, does not require wrong-way wiring, and achieves a higher percent of redundant vias. Addition of local loops does not impact timing or wireability of the design.